Owners manual

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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 457
shifted out all the bits. Writing 1 to this bit clears it.
0: Busy
1: Transfer Completed
11
R/W
0
TF_UDF
TXFIFO Underrun
This bit is set when if the TXFIFO is underrun. Writing 1 to this bit clears it.
0: TXFIFO is not underrun
1: TXFIFO is underrun
10
R/W
0
TF_OVF
TXFIFO Overflow
This bit is set when if the TXFIFO is overflow. Writing 1 to this bit clears it.
0: TXFIFO is not overflow
1: TXFIFO is overflowed
9
R/W
0
RX_UDF
RXFIFO Underrun
When set, this bit indicates that RXFIFO has underrun. Writing 1 to this bit
clears it.
8
R/W
0
RX_OVF
RXFIFO Overflow
When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit
clears it.
0: RXFIFO is available.
1: RXFIFO has overflowed.
7
/
/
/
6
R/W
0
TX_FULL
TXFIFO Full
This bit is set when if the TXFIFO is full . Writing 1 to this bit clears it.
0: TXFIFO is not Full
1: TXFIFO is Full
5
R/W
1
TX_EMP
TXFIFO Empty
This bit is set if the TXFIFO is empty. Writing 1 to this bit clears it.
0: TXFIFO contains one or more words.
1: TXFIFO is empty
4
R/W
0
TX_READY
TXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
1: TX_WL <= TX_TRIG_LEVEL
This bit is set any time if TX_WL <= TX_TRIG_LEVEL. Writing “1” to this bit
clears it. Where TX_WL is the water level of RXFIFO
3
/
/
reserved
2
R/W
0
RX_FULL
RXFIFO Full
This bit is set when the RXFIFO is full . Writing 1 to this bit clears it.
0: Not Full
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