Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 458
1: Full
1
R/W
1
RX_EMP
RXFIFO Empty
This bit is set when the RXFIFO is empty . Writing 1 to this bit clears it.
0: Not empty
1: empty
0
R/W
0
RX_RDY
RXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
1: RX_WL >= RX_TRIG_LEVEL
This bit is set any time if RX_WL >= RX_TRIG_LEVEL. Writing “1” to this bit
clears it. Where RX_WL is the water level of RXFIFO.
8.2.5.5. SPI FIFO Control Register(Default Value: 0x00400001)
Offset: 0x18
Register Name: SPI_ FCR
Bit
R/W
Default/Hex
Description
31
R/W
0
TX_FIFO_RST
TX FIFO Reset
Write ‘1’ to this bit will reset the control portion of the TX FIFO and auto
clear to ‘0’ when completing reset operation, write to ‘0’ has no effect.
30
R/W
0
TF_TEST_ENB
TX Test Mode Enable
0: disable
1: enable
Note: In normal mode, TX FIFO can only be read by SPI controller, write ‘1’
to this bit will switch TX FIFO read and write function to AHB bus. This bit is
used to test the TX FIFO, don’t set in normal operation and don’t set
RF_TEST and TF_TEST at the same time.
29:26
/
/
/
25
/
/
/
24
R/W
0x0
TF_ DRQ_EN
TX FIFO DMA Request Enable
0: Disable
1: Enable
23:16
R/W
0x40
TX_TRIG_LEVEL
TX FIFO Empty Request Trigger Level
15
R/W
0x0
RF_RST
RXFIFO Reset
Write ‘1’ to this bit will reset the control portion of the receiver FIFO, and
auto clear to ‘0’ when completing reset operation, write ‘0’ to this bit has no
effect.
14
R/W
0x0
RF_TEST
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