Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 459
RX Test Mode Enable
0: Disable
1: Enable
Note: In normal mode, RX FIFO can only be written by SPI controller, write
‘1’ to this bit will switch RX FIFO read and write function to AHB bus. This bit
is used to test the RX FIFO, don’t set in normal operation and don’t set
RF_TEST and TF_TEST at the same time.
13:10
R
0x0
Reserved
9
R/W
0x0
RX_DMA_MODE
SPI RX DMA Mode Control
0: Normal DMA mode
1: Dedicate DMA mode
8
R/W
0x0
RF_ DRQ_EN
RX FIFO DMA Request Enable
0: Disable
1: Enable
7:0
R/W
0x1
RX_TRIG_LEVEL
RX FIFO Ready Request Trigger Level
8.2.5.6. SPI FIFO Status Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: SPI_FSR
Bit
R/W
Default/Hex
Description
31
R
0x0
TB_WR
TX FIFO Write Buffer Write Enable
30:28
R
0x0
TB_CNT
TX FIFO Write Buffer Counter
These bits indicate the number of words in TX FIFO Write Buffer
27:24
R
0x0
Reserved
23:16
R
0x0
TF_CNT
TX FIFO Counter
These bits indicate the number of words in TX FIFO
0: 0 byte in TX FIFO
1: 1 byte in TX FIFO
…
64: 64 bytes in TX FIFO
15
R
0x0
RB_WR
RX FIFO Read Buffer Write Enable
14:12
R
0x0
RB_CNT
RX FIFO Read Buffer Counter
These bits indicate the number of words in RX FIFO Read Buffer
11:8
R
0x0
Reserved
7:0
R
0x0
RF_CNT
RX FIFO Counter
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