Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 460
These bits indicate the number of words in RX FIFO
0: 0 byte in RX FIFO
1: 1 byte in RX FIFO
…
64:64 bytes in RX FIFO
8.2.5.7. SPI Wait Clock Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: SPI_WAIT
Bit
R/W
Default/Hex
Description
31:20
/
/
/
19:16
R/W
0x0
SWC
Dual mode direction switch wait clock counter (for master mode only).
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Note: These bits control the number of wait states to be inserted before
start dual data transfer in dual SPI mode. The SPI module counts SPI_SCLK
by SWC for delaying next word data transfer.
Note：Can’t be written when XCH=1.
15:0
R/W
0
WCC
Wait Clock Counter (In Master mode)
These bits control the number of wait states to be inserted in data transfers.
The SPI module counts SPI_SCLK by WCC for delaying next word data
transfer.
0: No wait states inserted
N: N SPI_SCLK wait states inserted
8.2.5.8. SPI Clock Control Register(Default Value: 0x00000002)
Offset: 0x24
Register Name: SPI_CCTL
Bit
R/W
Default/Hex
Description
31:13
/
/
/
12
R/W
0
DRS
Divide Rate Select (Master Mode Only)
0: Select Clock Divide Rate 1
1: Select Clock Divide Rate 2
11:8
R/W
0
CDR1
Clock Divide Rate 1 (Master Mode Only)
The SPI_SCLK is determined according to the following equation: SPI_CLK =
Source_CLK / 2^n.
7:0
R/W
0x2
CDR2
Clock Divide Rate 2 (Master Mode Only)
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