Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 461
The SPI_SCLK is determined according to the following equation: SPI_CLK =
Source_CLK / (2*(n + 1)).
8.2.5.9. SPI Master Burst Counter Register(Default Value: 0x00000000)
Offset: 0x30
Register Name: SPI_BC
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:0
R/W
0
MBC
Master Burst Counter
In master mode, this field specifies the total burst number.
0: 0 burst
1: 1 burst
…
N: N bursts
8.2.5.10. SPI Master Transmit Counter Register(Default Value: 0x00000000)
Offset: 0x34
Register Name: SPI_TC
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:0
R/W
0
MWTC
Master Write Transmit Counter
In master mode, this field specifies the burst number that should be sent to
TXFIFO before automatically sending dummy burst. For saving bus
bandwidth, the dummy burst (all zero bits or all one bits) is sent by SPI
Controller automatically.
0: 0 burst
1: 1 burst
…
N: N bursts
8.2.5.11. SPI Master Burst Control Counter Register(Default Value: 0x00000000)
Offset: 0x38
Register Name: SPI_BCC
Bit
R/W
Default/Hex
Description
31:29
R
0x0
Reserved
28
R/W
0x0
DRM
Master Dual Mode RX Enable
0: RX use single-bit mode
1: RX use dual mode
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