Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 462
Note：Can’t be written when XCH=1.
27:24
R/W
0x0
DBC
Master Dummy Burst Counter
In master mode, this field specifies the burst number that should be sent
before receive in dual SPI mode. The data is don’t care by the device.
0: 0 burst
1: 1 burst
…
N: N bursts
Note：Can’t be written when XCH=1.
23:0
R/W
0x0
STC
Master Single Mode Transmit Counter
In master mode, this field specifies the burst number that should be sent in
single mode before automatically sending dummy burst. This is the first
transmit counter in all bursts.
0: 0 burst
1: 1 burst
…
N: N bursts
Note：Can’t be written when XCH=1.
8.2.5.12. SPI TX Data Register(Default Value: 0x00000000)
Offset: 0x200
Register Name: SPI_TXD
Bit
R/W
Default/Hex
Description
31:0
W/R
0x0
TDATA
Transmit Data
This register can be accessed in byte, half-word or word unit by AHB. In byte
accessing method, if there are rooms in RXFIFO, one burst data is written to
RXFIFO and the depth is increased by 1. In half-word accessing method, two
SPI burst data are written and the TXFIFO depth is increase by 2. In word
accessing method, four SPI burst data are written and the TXFIFO depth is
increased by 4.
Note: This address is writing-only if TF_TEST is ‘0’, and if TF_TEST is set to ‘1’,
this address is readable and writable to test the TX FIFO through the AHB
bus.
8.2.5.13. SPI RX Data Register(Default Value: 0x00000000)
Offset: 0x300
Register Name: SPI_RXD
Bit
R/W
Default/Hex
Description
31:0
R
0
RDATA
Receive Data
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