Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 466
8.3.4. UART Controller Register List
There are 5 UART controllers. All UART controllers can be configured as Serial IrDA.
Module Name
Base Address
UART0
0x01C28000
UART1
0x01C28400
UART2
0x01C28800
UART3
0x01C28C00
R-UART
0x01F02800
Register Name
Offset
Description
UART_RBR
0x00
UART Receive Buffer Register
UART_THR
0x00
UART Transmit Holding Register
UART_DLL
0x00
UART Divisor Latch Low Register
UART_DLH
0x04
UART Divisor Latch High Register
UART_IER
0x04
UART Interrupt Enable Register
UART_IIR
0x08
UART Interrupt Identity Register
UART_FCR
0x08
UART FIFO Control Register
UART_LCR
0x0C
UART Line Control Register
UART_MCR
0x10
UART Modem Control Register
UART_LSR
0x14
UART Line Status Register
UART_MSR
0x18
UART Modem Status Register
UART_SCH
0x1C
UART Scratch Register
UART_USR
0x7C
UART Status Register
UART_TFL
0x80
UART Transmit FIFO Level
UART_RFL
0x84
UART_RFL
UART_HALT
0xA4
UART Halt TX Register
8.3.5. UART Register Description
8.3.5.1. UART Receiver Buffer Register(Default Value: 0x00000000)
Offset: 0x0000
Register Name: UART_RBR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R
0
RBR
Receiver Buffer Register
Data byte received on the serial input port . The data in this register is valid
only if the Data Ready (DR) bit in the Line Status Register (LCR) is set.
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