Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 467
If in FIFO mode and FIFOs are enabled (FCR[0] set to one), this register
accesses the head of the receive FIFO. If the receive FIFO is full and this
register is not read before the next data character arrives, then the data
already in the FIFO is preserved, but any incoming data are lost and an
overrun error occurs.
8.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000)
Offset: 0x0000
Register Name: UART_THR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
W
0
THR
Transmit Holding Register
Data to be transmitted on the serial output port . Data should only be
written to the THR when the THR Empty (THRE) bit (LSR[5]) is set.
If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, 16
number of characters of data may be written to the THR before the FIFO is
full. Any attempt to write data when the FIFO is full results in the write data
being lost.
8.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000)
Offset: 0x0000
Register Name: UART_DLL
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R/W
0
DLL
Divisor Latch Low
Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the
baud rate divisor for the UART. This register may only be accessed when the
DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero).
The output baud rate is equal to the serial clock (sclk) frequency divided by
sixteen times the value of the baud rate divisor, as follows: baud rate =
(serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the
baud clock is disabled and no serial communications occur. Also, once the
DLL is set, at least 8 clock cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving data.
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