Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 468
8.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000)
Offset: 0x0004
Register Name: UART_DLH
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R/W
0
DLH
Divisor Latch High
Upper 8 bits of a 16-bit, read/write, Divisor Latch register that contains the
baud rate divisor for the UART. This register may only be accessed when the
DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero).
The output baud rate is equal to the serial clock (sclk) frequency divided by
sixteen times the value of the baud rate divisor, as follows: baud rate =
(serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the
baud clock is disabled and no serial communications occur. Also, once the
DLH is set, at least 8 clock cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving data.
8.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x0004
Register Name: UART_IER
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
PTIME
Programmable THRE Interrupt Mode Enable
This is used to enable/disable the generation of THRE Interrupt.
0: Disable
1: Enable
6:4
/
/
/
3
R/W
0
EDSSI
Enable Modem Status Interrupt
This is used to enable/disable the generation of Modem Status Interrupt.
This is the fourth highest priority
interrupt.
0: Disable
1: Enable
2
R/W
0
ELSI
Enable Receiver Line Status Interrupt
This is used to enable/disable the generation of Receiver Line Status
Interrupt. This is the highest priority interrupt.
0: Disable
1: Enable
1
R/W
0
ETBEI
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