Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 469
Enable Transmit Holding Register Empty Interrupt
This is used to enable/disable the generation of Transmitter Holding Register
Empty Interrupt. This is the third highest priority interrupt.
0: Disable
1: Enable
0
R/W
0
ERBFI
Enable Received Data Available Interrupt
This is used to enable/disable the generation of Received Data Available
Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs
enabled). These are the second highest priority interrupts.
0: Disable
1: Enable
8.3.5.6. UART Interrupt Identity Register(Default Value: 0x00000000)
Offset: 0x0008
Register Name: UART_IIR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:6
R
0
FEFLAG
FIFOs Enable Flag
This is used to indicate whether the FIFOs are enabled or disabled.
00: Disable
11: Enable
5:4
/
/
/
3:0
R
0x1
IID
Interrupt ID
This indicates the highest priority pending interrupt which can be one of the
following types:
0000: modem status
0001: no interrupt pending
0010: THR empty
0100: received data available
0110: receiver line status
0111: busy detect
1100: character timeout
Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and
used to distinguish a Character Timeout condition interrupt.
Interru
pt ID
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset
0001
-
None
None
-
0110
Highest
Receiver line
status
Overrun/parity/ framing errors
or break interrupt
Reading the line status register
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