Owners manual
H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 47
8.9.4.1. Basic Control 0 Register(Default Value: 0x00000000) .............................................................. 572
8.9.4.2. Basic Control 1 Register(Default Value: 0x08000000) .............................................................. 572
8.9.4.3. Interrupt Status Register(Default Value: 0x00000000) ............................................................. 573
8.9.4.4. Interrupt Enable Register(Default Value: 0x00000000) ............................................................ 574
8.9.4.5. Transmit Control 0 Register(Default Value: 0x00000000) ......................................................... 575
8.9.4.6. Transmit Control 1 Register(Default Value: 0x00000000) ......................................................... 575
8.9.4.7. Transmit Flow Control Register(Default Value: 0x00000000) ................................................... 576
8.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000) .......................... 577
8.9.4.9. Receive Control 0 Register(Default Value: 0x00000000) .......................................................... 577
8.9.4.10. Receive Control 1 Register(Default Value: 0x00000000) ........................................................ 577
8.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000) ......................... 579
8.9.4.12. Receive Frame Filter Register(Default Value: 0x00000000) ................................................... 579
8.9.4.13. Receive Hash Table 0 Register(Default Value: 0x00000000) ................................................... 580
8.9.4.14. Receive Hash Table 1 Register(Default Value: 0x00000000) ................................................... 580
8.9.4.15. MII Command Register(Default Value: 0x00000000) ............................................................. 581
8.9.4.16. MII Data Register(Default Value: 0x00000000) ....................................................................... 581
8.9.4.17. MAC Address 0 High Register(Default Value: 0x0000FFFF) .................................................... 581
8.9.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF) ...................................................... 582
8.9.4.19. MAC Address x High Register(Default Value: 0x0000FFFF) ..................................................... 582
8.9.4.20. MAC Address x Low Register(Default Value: 0xFFFFFFFF) ...................................................... 582
8.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000) ................................................... 583
8.9.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000) ............................... 583
8.9.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000) ........................ 583
8.9.4.24. Receive DMA Status Register(Default Value: 0x00000000) .................................................... 583
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