Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 470
0100
Second
Received data
available
Receiver data available
(non-FIFO mode or FIFOs
disabled) or RCVR FIFO trigger
level reached (FIFO mode and
FIFOs enabled)
Reading the receiver buffer register
(non-FIFO mode or FIFOs disabled) or the
FIFO drops below the trigger level (FIFO
mode and FIFOs enabled)
1100
Second
Character
timeout
indication
No characters in or out of the
RCVR FIFO during the last 4
character times and there is at
least 1character in it during
This time
Reading the receiver buffer register
0010
Third
Transmit
holding register
empty
Transmitter holding register
empty (Program THRE Mode
disabled) or XMIT FIFO at or
below threshold (Program
THRE Mode enabled)
Reading the IIR register (if source of
interrupt); or, writing into THR (FIFOs or
THRE Mode not selected or disabled) or
XMIT FIFO above threshold (FIFOs and
THRE Mode selected and enabled).
0000
Fourth
Modem status
Clear to send or data set ready
or ring indicator or data carrier
detect. Note that if auto flow
control mode is enabled, a
change in CTS (that is, DCTS
set) does not cause an
interrupt.
Reading the Modem status Register
0111
Fifth
Busy detect
indication
UART_16550_COMPATIBLE =
NO and master has tried to
write to the Line Control
Register while the UART is busy
(USR[0] is set to one).
Reading the UART status register
8.3.5.7. UART FIFO Control Register(Default Value: 0x00000000)
Offset: 0x0008
Register Name: UART_FCR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:6
W
0
RT
RCVR Trigger
This is used to select the trigger level in the receiver FIFO at which the
Received Data Available Interrupt is generated. In auto flow control mode it
is used to determine when the rts_n signal is de-asserted. It also determines
when the dma_rx_req_n signal is asserted in certain modes of operation.
00: 1 character in the FIFO
01: FIFO ¼ full
10: FIFO ½ full
11: FIFO-2 less than full
5:4
W
0
TFT
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