Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 471
TX Empty Trigger
Writes have no effect when THRE_MODE_USER = Disabled. This is used to
select the empty threshold level at which the THRE Interrupts are generated
when the mode is active. It also determines when the dma_tx_req_n signal
is asserted when in certain modes of operation.
00: FIFO empty
01: 2 characters in the FIFO
10: FIFO ¼ full
11: FIFO ½ full
3
W
0
DMAM
DMA Mode
0: Mode 0
1: Mode 1
2
W
0
XFIFOR
XMIT FIFO Reset
This resets the control portion of the transmit FIFO and treats the FIFO as
empty. This also de-asserts the DMA TX request.
It is 'self-clearing'. It is not necessary to clear this bit.
1
W
0
RFIFOR
RCVR FIFO Reset
This resets the control portion of the receive FIFO and treats the FIFO as
empty. This also de-asserts the DMA RX request.
It is 'self-clearing'. It is not necessary to clear this bit.
0
W
0
FIFOE
Enable FIFOs
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs.
Whenever the value of this bit is changed both the XMIT and RCVR
controller portion of FIFOs is reset.
8.3.5.8. UART Line Control Register(Default Value: 0x00000000)
Offset: 0x000C
Register Name: UART_LCR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0
DLAB
Divisor Latch Access Bit
It is writeable only when UART is not busy (USR[0] is zero) and always
readable. This bit is used to enable reading and writing of the Divisor Latch
register (DLL and DLH) to set the baud rate of the UART. This bit must be
cleared after initial baud rate setup in order to access other registers.
0: Select RX Buffer Register (RBR) / TX Holding Register(THR) and Interrupt
Enable Register (IER)
1: Select Divisor Latch LS Register (DLL) and Divisor Latch MS Register (DLM)
6
R/W
0
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