Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 474
value written to this location is inverted and driven out on dtr_n.
0：dtr_n de-asserted (logic 1)
1：dtr_n asserted (logic 0)
The Data Terminal Ready output is used to inform the modem or data set
that the UART is ready to establish communications.
Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held
inactive high while the value of this location is internally looped back to an
input.
8.3.5.10. UART Line Status Register(Default Value: 0x00000060)
Offset: 0x0014
Register Name: UART_LSR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R
0
FIFOERR
RX Data Error in FIFO
When FIFOs are disabled, this bit is always 0. When FIFOs are enabled, this
bit is set to 1 when there is at least one PE, FE, or BI in the RX FIFO. It is
cleared by a read from the LSR register provided there are no subsequent
errors in the FIFO.
6
R
1
TEMT
Transmitter Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register and the TX Shift Register are empty. If the FIFOs are enabled, this
bit is set whenever the TX FIFO and the TX Shift Register are empty. In both
cases, this bit is cleared when a byte is written to the TX data channel.
5
R
1
THRE
TX Holding Register Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register is empty and ready to accept new data and it is cleared when the
CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to "1" whenever the TX FIFO is empty
and it is cleared when at least one byte is written
to the TX FIFO.
4
R
0
BI
Break Interrupt
This is used to indicate the detection of a break sequence on the serial input
data.
It is set whenever the serial input, sin, is held in a logic '0' state for longer
than the sum of start time + data bits + parity + stop bits.
In the FIFO mode, the character associated with the break condition is
carried through the FIFO and is revealed when the character is at the top of
the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI
indication occurs immediately and persists until the LSR is read.
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