Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 478
Scratch Register
This register is for programmers to use as a temporary storage space. It has
no defined purpose in the UART.
8.3.5.13. UART Status Register(Default Value: 0x00000006)
Offset: 0x007C
Register Name: UART_USR
Bit
R/W
Default/Hex
Description
31:5
/
/
/
4
R
0
RFF
Receive FIFO Full
This is used to indicate that the receive FIFO is completely full.
0: Receive FIFO not full
1: Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.
3
R
0
RFNE
Receive FIFO Not Empty
This is used to indicate that the receive FIFO contains one or more entries.
0: Receive FIFO is empty
1: Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
2
R
1
TFE
Transmit FIFO Empty
This is used to indicate that the transmit FIFO is completely empty.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.
1
R
1
TFNF
Transmit FIFO Not Full
This is used to indicate that the transmit FIFO in not full.
0: Transmit FIFO is full
1: Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0
R
0
BUSY
UART Busy Bit
0: Idle or inactive
1: Busy
8.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x00000000)
Offset: 0x0080
Register Name: UART_TFL
Bit
R/W
Default/Hex
Description
confidential