Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 479
31:7
/
/
/
6:0
R
0
TFL
Transmit FIFO Level
This is indicates the number of data entries in the transmit FIFO.
8.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000)
Offset: 0x0084
Register Name: UART_RFL
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6:0
R
0
RFL
Receive FIFO Level
This is indicates the number of data entries in the receive FIFO.
8.3.5.16. UART Halt TX Register(Default Value: 0x00000000)
Offset: 0x00A4
Register Name: UART_HALT
Bit
R/W
Default/Hex
Description
31:4
/
/
/
5
R/W
0
SIR_RX_INVERT
SIR Receiver Pulse Polarity Invert
0: Not invert receiver signal
1: Invert receiver signal
4
R/W
0
SIR_TX_INVERT
SIR Transmit Pulse Polarity Invert
0: Not invert transmit pulse
1: Invert transmit pulse
3
/
/
/
2
R/W
0
CHANGE_UPDATE
After the user using HALT[1] to change the baudrate or LCR configuration,
write 1 to update the configuration and waiting this bit self clear to 0 to
finish update process. Write 0 to this bit has no effect.
1: Update trigger, Self clear to 0 when finish update.
1
R/W
0
CHCFG_AT_BUSY
This is an enable bit for the user to change LCR register configuration
(except for the DLAB bit) and baudrate register (DLH and DLL) when the
UART is busy (USB[0] is 1).
1: Enable change when busy
0
R/W
0
HALT_TX
Halt TX
This register is use to halt transmissions for testing, so that the transmit FIFO
can be filled by the master when FIFOs are implemented and enabled.
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