Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 481
8.4. CIR Receiver
8.4.1. Overview
The CIR includes the following features:
 Full physical layer implementation
 Support CIR for remote control
 64x8 bits FIFO for data buffer
 Programmable FIFO thresholds
For saving CPU resource, CIR receiver is implemented in hardware. The CIR receiver samples the input signal on the
programmable frequency and records these samples into RX FIFO when one CIR signal is found on the air. The CIR
receiver uses Run-Length Code (RLC) to encode pulse width. The encoded data is buffered in a 64 levels and 8-bit width
RX FIFO; the MSB bit is used to record the polarity of the receiving CIR signal. The high level is represented as ‘1’ and the
low level is represented as ‘0’. The rest 7 bits are used for the length of RLC. The maximum length is 128. If the duration
of one level (high or low level) is more than 128, another byte is used.
In the air, there is always some noise. One threshold can be set to filter the noise to reduce system loading and improve
the system stability.
8.4.2. CIR Receiver Register List
Module Name
Base Address
CIR
0x01F02000
Register Name
Offset
Description
CIR_CTL
0x00
CIR Control Register
CIR_RXCTL
0x10
CIR Receiver Configure Register
CIR_RXFIFO
0x20
CIR Receiver FIFO Register
CIR_RXINT
0x2C
CIR Receiver Interrupt Control Register
CIR_RXSTA
0x30
CIR Receiver Status Register
CIR_CONFIG
0x34
CIR Configure Register
confidential