Owners manual

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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 482
8.4.3. CIR Receiver Register Description
8.4.3.1. CIR Receiver Control Register(Default Value: 0x00000000)
Offset: 0x0000
Register Name: CIR_CTL
Bit
R/W
Default/Hex
Description
31:9
/
/
/
8
R/W
0
CGPO
General Program Output (GPO) Control in CIR mode for TX Pin
0: Low level
1: High level
7:6
/
/
/
5:4
R/W
0
CIR ENABLE
00~10: Reserved
11: CIR mode enable
3:2
/
/
/.
1
R/W
0
RXEN
Receiver Block Enable
0: Disable
1: Enable
0
R/W
0
GEN
Global Enable
A disable on this bit overrides any other block or channel enables and
flushes all FIFOs.
0: Disable
1: Enable
8.4.3.2. CIR Receiver Configure Register(Default Value: 0x00000004)
Offset: 0x0010
Register Name: CIR_RXCTL
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
1
RPPI
Receiver Pulse Polarity Invert
0: Not invert receiver signal
1: Invert receiver signal
1:0
/
/
/
8.4.3.3. CIR Receiver FIFO Register(Default Value: 0x00000000)
Offset: 0x0020
Register Name: CIR_RXFIFO
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