Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 483
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R
0
Receiver Byte FIFO
8.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x002C
Register Name: CIR_RXINT
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13:8
R/W
0
RAL
RX FIFO Available Received Byte Level for interrupt and DMA request
TRIGGER_LEVEL = RAL + 1
5
R/W
0
DRQ_EN
RX FIFO DMA Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO DRQ is asserted if reaching RAL. The DRQ
is de-asserted when condition fails.
4
R/W
0
RAI_EN
RX FIFO Available Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO IRQ is asserted if reaching RAL. The IRQ is
de-asserted when condition fails.
3:2
/
/
/
1
R/W
0
RPEI_EN
Receiver Packet End Interrupt Enable
0: Disable
1: Enable
0
R/W
0
ROI_EN
Receiver FIFO Overrun Interrupt Enable
0: Disable
1: Enable
8.4.3.5. CIR Receiver Status Register(Default Value: 0x00000000)
Offset: 0x0030
Register Name: CIR_RXSTA
Bit
R/W
Default/Hex
Description
31:15
/
/
/
14:8
R
0
RAC
RX FIFO Available Counter
0: No available data in RX FIFO
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