Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 484
1: 1 byte available data in RX FIFO
2: 2 byte available data in RX FIFO
…
64: 64 byte available data in RX FIFO
7
R
0x0
STAT
Status of CIR
0x0 – Idle
0x1 – busy
6:5
/
/
/
4
R/W
0
RA
RX FIFO Available
0: RX FIFO not available according its level
1: RX FIFO available according its level
This bit is cleared by writing a ‘1’.
3:2
/
/
/
1
R/W
0
RPE
Receiver Packet End Flag
0: STO was not detected. In CIR mode, one CIR symbol is receiving or not
detected.
1: STO field or packet abort symbol (7’b0000,000 and 8’b0000,0000 for MIR
and FIR) is detected. In CIR mode, one CIR symbol is received.
This bit is cleared by writing a ‘1’.
0
R/W
0
ROI
Receiver FIFO Overrun
0: Receiver FIFO not overrun
1: Receiver FIFO overrun
This bit is cleared by writing a ‘1’.
8.4.3.6. CIR Receiver Configure Register(Default Value: 0x00000000)
Offset: 0x0034
Register Name: CIR_RCR
Bit
R/W
Default/Hex
Description
31
/
/
/
30:25
/
/
/
24
R/W
0x0
SCS2
Bit2 of Sample Clock Select for CIR
This bit is defined by SCS bits below.
23
R/W
0x0
ATHC
Active Threshold Control for CIR
0x0 –ATHR in Unit of (Sample Clock)
0x1 –ATHR in Unit of (128*Sample Clocks)
22:16
R/W
0x0
ATHR
Active Threshold for CIR
These bits control the duration of CIR from Idle to Active State. The duration
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