Owners manual

Interfaces

8.5. USB

8.5.1. USB OTG Controller

8.5.1.1. Overview

The USB OTG is a Dual-Role Device controller, which supports both device and host functions which can also be

configured as a Host-only or Device-only controller, fully compliant with the USB 2.0 Specification. It can support

high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers in Host mode. It can

support high-speed (HS, 480-Mbps), and full-speed (FS, 12-Mbps) in Device mode. Standard USB transceiver can be

used through its UTMI+PHY Level3 interface. The UTMI+PHY interface is bidirectional with 8-bit data bus. For saving

CPU bandwidth, USB-OTG DMA interface can support external DMA controller to take care of the data transfer between

the memory and USB-OTG FIFO. The USB-OTG core also supports USB power saving functions.

The USB2.0 OTG controller has following features:

 Complies with USB 2.0 Specification

 Support Device or Host operation at a time

 Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in host mode

 Complies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and the Open Host Controller

Interface (OHCI) Specification, Version 1.0a for host mode

 Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in device mode

 Supports bi-directional endpoint0 for Control transfer in device mode

 Supports up to 8 User-Configurable Endpoints for Bulk , Isochronousl and Interrupt bi-directional transfers

(Endpoint1, Endpoint2, Endpoint3, Endpoint4, Endpoint5) in device mode

 Supports up to (4KB+64B) FIFO for EPs (Excluding EP0) in device mode

 Supports the UTMI+ Level 3 interface . The 8-bit bidirectional data buses are used

 Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral mode

 Power Optimization and Power Management capabilities

8.5.1.2. Block Diagram

Figure 8-6 shows the block diagram of USB OTG Controller:

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