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H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 49
8.10.4.14. TSF Control and Status Register(Default Value: 0x00000000) ............................................... 598
8.10.4.15. TSF Packet Parameter Register(Default Value: 0x00470000) ................................................ 598
8.10.4.16. TSF Interrupt Enable and Status Register(Default Value: 0x00000000) ................................ 599
8.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000) ......................................... 600
8.10.4.18. TSF Overlap Interrupt Enable Register(Default Value: 0x00000000) ..................................... 600
8.10.4.19. TSF DMA Interrupt Status Register(Default Value: 0x00000000) .......................................... 600
8.10.4.20. TSF Overlap Interrupt Status Register(Default Value: 0x00000000) ...................................... 600
8.10.4.21. TSF PCR Control Register(Default Value: 0x00000000) ......................................................... 601
8.10.4.22. TSF PCR Data Register(Default Value: 0x00000000) .............................................................. 601
8.10.4.23. TSF Channel Enable Register(Default Value: 0x00000000).................................................... 601
8.10.4.24. TSF PES Enable Register(Default Value: 0x00000000) ........................................................... 602
8.10.4.25. TSF Channel Descramble Enable Register(Default Value: 0x00000000) ................................ 602
8.10.4.26. TSF Channel Index Register(Default Value: 0x00000000) ...................................................... 602
8.10.4.27. TSF Channel Control Register(Default Value: 0x00000000)................................................... 602
8.10.4.28. TSF Channel Status Register(Default Value: 0x00000000) .................................................... 603
8.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000) ............................................... 603
8.10.4.30. TSF Channel PID Register(Default Value: 0x1FFF0000) ......................................................... 603
8.10.4.31. TSF Channel Buffer Base Address Register(Default Value: 0x00000000) .............................. 603
8.10.4.32. TSF Channel Buffer Size Register(Default Value: 0x00000000) ............................................. 604
8.10.4.33. TSF Channel Write Pointer Register(Default Value: 0x00000000) ......................................... 604
8.10.4.34. TSF Channel Read Pointer Register(Default Value: 0x00000000) .......................................... 604
8.10.4.35. TSD Control Register(Default Value: 0x00000000) ................................................................ 605
8.10.4.36. TSD Status Register(Default Value: 0x00000000) .................................................................. 605
8.10.4.37. TSD Control Word Index Register(Default Value: 0x00000000) ............................................ 605
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