Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 491
to system software.
This field will always fix with ‘0’.
7
R
0
Port Routing Rules
This field indicates the method used by this implementation for how all
ports are mapped to companion controllers. The value of this field has the
following interpretation:
Value
Meaning
0
The first N_PCC ports are routed to the lowest numbered
function companion host controller, the next N_PCC port
are routed to the next lowest function companion
controller, and so on.
1
The port routing is explicitly enumerated by the first
N_PORTS elements of the HCSP-PORTTOUTE array.
This field will always be ‘0’.
6:4
/
0
Reserved.
These bits are reserved and should be set to zero.
3:0
R
1
N_PORTS
This field specifies the number of physical downstream ports implemented
on this host controller. The value of this field determines how many port
registers are addressable in the Operational Register Space. Valid values are
in the range of 0x1 to 0x0f.
This field is always 1.
8.5.2.5.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation Dependent)
Offset: 0x0008
Register Name: HCCPARAMS
Bit
R/W
Default/Hex
Description
31:16
/
0
Reserved
These bits are reserved and should be set to zero.
15:18
R
0
EHCI Extended Capabilities Pointer (EECP)
This optional field indicates the existence of a capabilities list. A value of 00b
indicates no extended capabilities are implemented. A non-zero value in this
register indicates the offset in PCI configuration space of the first EHCI
extended capabiliby. The pointer value must be 40h or greater if
implemented to maintain to consistency of the PCI header defined for this
calss of device.
The value of this field is always ‘00b’.
7:4
R
Isochronous Scheduling Threshold
This field indicates, relative to the current position of the executing host
controller, where software can reliably update the isochronous schedule.
When bit[7] is zero, the value of the least significant 3 bits indicates the
number of micro-frames a host controller can hold a set of isochronous data
structures(one or more) before flushing the state. When bit[7] is a one, then
host software assumes the host controller may cache an isochronous data
confidential