Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 494
7
R/W
0
Light Host Controller Reset(OPTIONAL)
This control bit is not required.
If implemented, it allows the driver to reset the EHCI controller without
affecting the state of the ports or relationship to the companion host
controllers. For example, the PORSTC registers should not be reset to their
default values and the CF bit setting should not go to zero (retaining port
ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it si safe for software to re-initialize the host
controller. A host software read of this bit as a one indicates the Light Host
6
R/W
0
Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller to issue
an interrupt the next time it advances asynchronous schedule. Soft-
Ware must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule state,
it sets the Interrupt on Async Advance status bit in the USBSTS. if the
Interrupt on Async Advance Enable bit in the USBINTR register is a one then
the host controller will assert an interrupt at the next interrupt threshold.
The host controller sets this bit to a zero after it has set the Interrupt on
Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous schedule
is disabled. Doing so will yield undefined results.
5
R/W
0
Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
Bit Value
Meaning
0
Do not process the Asynchronous Schedule.
1
Use the ASYNLISTADDR register to access the
Asynchronous Schedule.
The default value of this field is ‘0b’.
4
R/W
0
Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic
Schedule. Values mean:
Bit Value
Meaning
0
Do not process the Periodic Schedule.
1
Use the PERIODICLISTBASE register to access the
Periodic Schedule.
The default value of this field is ‘0b’.
3:2
R/W or
R
0
Frame List Size
This field is R/W only if Programmable Frame List Flag in the HCCPARAMS
registers is set to a one. This field specifies the size of the
Frame list. The size the frame list controls which bits in the Frame Index
Register should be used for the Frame List Current index. Values mean:
Bits
Meaning
00b
1024 elements(4096bytes)Default
confidential