Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 495
01b
512 elements(2048byts)
10b
256 elements(1024bytes)For resource-constrained condition
11b
reserved
The default value is ‘00b’.
1
R/W
0
Host Controller Reset
This control bit is used by software to reset the host controller. The effects of
this on Root Hub registers are similar to a Chip Hardware Reset.
When software writes a one to this bit, the Host Controller resets its internal
pipelines, timers, counters, state machines, etc. to their initial value. Any
transaction currently in progress on USB is immediately terminated. A USB
reset is not driven on downstream ports.
All operational registers, including port registers and port state machines are
set to their initial values. Port ownership reverts to the companion host
controller(s). Software must reinitialize the host controller as described in
Section 4.1 of the CHEI Specification in order to return the host controller to
an operational state.
This bit is set to zero by the Host Controller when the reset process is
complete. Software cannot terminate the reset process early by writing a
zero to this register.
Software should not set this bit to a one when the HC Halted bit in the
USBSTS register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
0
R/W
0
Run/Stop
When set to a 1, the Host Controller proceeds with execution of the
schedule. When set to 0, the Host Controller completes the current and any
actively pipelined transactions on the USB and then halts. The Host
Controller must halt within 16 micro-frames after software clears this bit.
The HC Halted bit indicates when the Host Controller has finished its
pending pipelined transactions and has entered the stopped state.
Software must not write a one to this field unless the Host Controller is in
the Halt State.
The default value is 0x0.
8.5.2.5.7. EHCI USB Status Register (Default Value: 0x00001000)
Offset: 0x0014
Register Name: USBSTS
Bit
R/W
Default/Hex
Description
31:16
/
0
Reserved
These bits are reserved and should be set to zero.
15
R
0
Asynchronous Schedule Status
The bit reports the current real status of Asynchronous Schedule. If this bit is
a zero then the status of the Asynchronous Schedule is disabled. If this bit is
a one then the status of the Asynchronous Schedule is enabled. The Host
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