Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 496
Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).
14
R
0
Periodic Schedule Status
The bit reports the current real status of the Periodic Schedule. If this bit is a
zero then the status of the Periodic Schedule is disabled. If this bit is a one
then the status of the Periodic Schedule is enabled. The Host Controller is
not required to immediately disable or enable the Periodic Schedule when
software transitions the Periodic Schedule Enable bit in the USBCMD
register. When this bit and the Periodic Schedule Enable bit are the same
value, the Periodic Schedule is either enabled (1) or disabled (0).
13
R
0
Reclamation
This is a read-only status bit, which is used to detect an empty asynchronous
schedule.
12
R
1
HC Halted
This bit is a zero whenever the Run/Stop bit is a one. The Host Controller
Sets this bit to one after it has stopped executing as a result of the Run/Stop
bit being set to 0, either by software or by the Host Controller Hardware
(e.g. internal error).
The default value is ‘1’.
11:6
/
0
Reserved
These bits are reserved and should be set to zero.
5
R/WC
0
Interrupt on Async Advance
System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD register.
This status bit indicates the assertion of that interrupt source.
4
R/WC
0
Host System Error
The Host Controller set this bit to 1 when a serious error occurs during a
host system access involving the Host Controller module. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command register
to prevent further execution of the scheduled TDs.
3
R/WC
0
Frame List Rollover
The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which the rollover
occurs depends on the frame list size. For example, if the frame list size is
1024, the Frame Index Register rolls over every time FRINDEX [13] toggles.
Similarly, if the size is 512, the Host Controller sets this bit to a one every
time FRINDEX [12] toggles.
2
R/WC
0
Port Change Detect
The Host Controller sets this bit to a one when any port for which the Port
Owner bit is set to zero has a change bit transition from a zero to a one or a
Force Port Resume bit transition from a zero to a one as a result of a J-K
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