Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 497
transition detected on a suspended port. This bit will also be set as a result
of the Connect Status Chang being set to a one after system software has
relinquished ownership of a connected port by writing a one to a port’s Port
Owner bit.
1
R/WC
0
USB Error Interrupt(USBERRINT)
The Host Controller sets this bit to 1 when completion of USB transaction
results in an error condition(e.g. error counter underflow).If the TD on
which the error interrupt occurred also had its IOC bit set, both.
This bit and USBINT bit are set.
0
R/WC
0
USB Interrupt(USBINT)
The Host Controller sets this bit to a one on the completion of a USB
transaction, which results in the retirement of a Transfer Descriptor that had
its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected
(actual number of bytes received was less than the expected number of
bytes)
8.5.2.5.8. EHCI USB Interrupt Enable Register (Default Value: 0x00000000)
Offset: 0x0018
Register Name: USBINTR
Bit
R/W
Default/Hex
Description
31:6
/
0
Reserved
These bits are reserved and should be zero.
5
R/W
0
Interrupt on Async Advance Enable
When this bit is 1, and the Interrupt on Async Advance bit in the USBSTS
register is 1, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software clearing the Interrupt
on Async Advance bit.
4
R/W
0
Host System Error Enable
When this bit is 1, and the Host System Error Status bit in the USBSTS
register is 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Host System Error bit.
3
R/W
0
Frame List Rollover Enable
When this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1,
the host controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Frame List Rollover bit.
2
R/W
0
Port Change Interrupt Enable
When this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1,
the host controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Port Chang Detect bit.
1
R/W
0
USB Error Interrupt Enable
When this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the
host controller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBERRINT bit.
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