Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 498
0
R/W
0
USB Interrupt Enable
When this bit is 1, and the USBINT bit in the USBSTS register is 1,the host
controller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBINT bit
8.5.2.5.9. EHCI Frame Index Register (Default Value: 0x00000000)
Offset: 0x001C
Register Name: FRINDEX
Bit
R/W
Default/Hex
Description
31:14
/
0
Reserved
These bits are reserved and should be zero.
13:0
R/W
0
Frame Index
The value in this register increment at the end of each time frame
(e.g. micro-frame).Bits[N:3] are used for the Frame List current index. It
Means that each location of the frame list is accessed 8 times(frames or
Micro-frames) before moving to the next index. The following illustrates
Values of N based on the value of the Frame List Size field in the USBCMD
register.
USBCMD[Frame List Size]
Number Elements
N
00b
1024
12
01b
512
11
10b
256
10
11b
Reserved
Note: This register must be written as a DWord. Byte writes produce undefined results.
8.5.2.5.10. EHCI Periodic Frame List Base Address Register (Default Value: Undefined)
Offset: 0x0024
Register Name: PERIODICLISTBASE
Bit
R/W
Default/Hex
Description
31:12
R/W
Base Address
These bits correspond to memory address signals [31:12], respectively.
This register contains the beginning address of the Periodic Frame List in the
system memory.
System software loads this register prior to starting the schedule execution
by the Host Controller. The memory structure referenced by this physical
memory pointer is assumed to be 4-K byte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable
the Host Controller to step through the Periodic Frame List in sequence.
11:0
/
Reserved
Must be written as 0x0 during runtime, the values of these bits are
undefined.
Note: Writes must be Dword Writes.
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