Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 499
8.5.2.5.11. EHCI Current Asynchronous List Address Register (Default Value: Undefined)
Offset: 0x0028
Register Name: ASYNCLISTADDR
Bit
R/W
Default/Hex
Description
31:5
R/W
Link Pointer (LP)
This field contains the address of the next asynchronous queue head to be
executed.
These bits correspond to memory address signals [31:5], respectively.
4:0
/
/
Reserved
These bits are reserved and their value has no effect on operation.
Bits in this field cannot be modified by system software and will always
return a zero when read.
Note: Write must be DWord Writes.
8.5.2.5.12. EHCI Configure Flag Register (Default Value: 0x00000000)
Offset: 0x0050
Register Name: CONFIGFLAG
Bit
R/W
Default/Hex
Description
31:1
/
0
Reserved
These bits are reserved and should be set to zero.
0
R/W
0
Configure Flag(CF)
Host software sets this bit as the last action in its process of configuring the
Host Controller. This bit controls the default port-routing control logic as
follow:
Value
Meaning
0
Port routing control logic default-routs each port to an
implementation dependent classic host controller.
1
Port routing control logic default-routs all ports to this host
controller.
The default value of this field is ‘0’.
Note: This register is not use in the normal implementation.
8.5.2.5.13. EHCI Port Status and Control Register (Default Value: 0x00002000(w/PPC set to one);0x00003000
(w/PPC set to a zero))
Offset: 0x0054
Register Name: PORTSC
Bit
R/W
Default/Hex
Description
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