Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 501
signal lines. These bits are used for detection of low-speed USB devices prior
to port reset and enable sequence. This read only field is valid only when
the port enable bit is zero and the current connect status bit is set to a one.
The encoding of the bits are:
Bit[11:10]
USB State
Interpretation
00b
SE0
Not Low-speed device, perform EHCI
reset.
10b
J-state
Not Low-speed device, perform EHCI
reset.
01b
K-state
Low-speed device, release ownership of
port.
11b
Undefined
Not Low-speed device, perform EHCI
reset.
This value of this field is undefined if Port Power is zero.
9
/
0
Reserved
This bit is reserved for future use, and should return a value of zero when
read.
8
R/W
0
Port Reset
1=Port is in Reset. 0=Port is not in Reset. Default = 0.
When software writes a one to this bit (from a zero), the bus reset sequence
as defined in the USB Specification Revision 2.0 is started. Software writes a
zero to this bit to terminate the bus reset sequence. Software must keep
this bit at a one long enough to ensure the reset sequence, as specified in
the USB Specification Revision 2.0, completes. Notes: when software writes
this bit to a one , it must also write a zero to the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay
before the bit status changes to a zero. The bit status will not read as a zero
until after the reset has completed. If the port is in high-speed mode after
reset is complete, the host controller will automatically enable this port (e.g.
set the Port Enable bit to a one). A host controller must terminate the reset
and stabilize the state of the port within 2 milliseconds of software
transitioning this bit from a one to a zero. For example: if the port detects
that the attached device is high-speed during reset, then the host controller
must have the port in the enabled state with 2ms of software writing this bit
to a zero.
The HC Halted bit in the USBSTS register should be a zero before software
attempts to use this bit. The host controller may hold Port Reset asserted to
a one when the HC Halted bit is a one.
This field is zero if Port Power is zero.
7
R/W
0
Suspend
Port Enabled Bit and Suspend bit of this register define the port states as
follows:
Bits[Port Enables, Suspend]
Port State
0x
Disable
10
Enable
confidential