Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 502
11
Suspend
When in suspend state, downstream propagation of data is blocked on this
port, except for port reset. The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1.
In the suspend state, the port is sensitive to resume detection. Not that the
bit status does not change until the port is suspend and that there may be a
delay in suspending a port if there is a transaction currently in progress on
the USB.
A write of zero to this bit is ignored by the host controller. The host
controller will unconditionally set this bit to a zero when:
① Software sets the Force Port Resume bit to a zero(from a one).
② Software sets the Port Reset bit to a one(from a zero).
If host software sets this bit to a one when the port is not enabled(i.e. Port
enabled bit is a zero), the results are undefined.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
6
R/W
0
Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-state) detected/
driven on port. Default = 0.
This functionality defined for manipulating this bit depends on the value of
the Suspend bit. For example, if the port is not suspend and software
transitions this bit to a one, then the effects on the bus are undefined.
Software sets this bit to a 1 drive resume signaling. The Host Controller sets
this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-K transition
is detected, the Port Change Detect bit in the USBSTS register is also set to a
one. If software sets this bit to a one, the host controller must not set the
Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification Revision
2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this
remains a one. Software must appropriately time the Resume and set this
bit to a zero when the appropriate amount of time has elapsed. Writing a
zero (from one) causes the port to return high-speed mode (forcing the bus
below the port into a high-speed idle). This bit will remain a one until the
port has switched to high-speed idle. The host controller must complete this
transition within 2 milliseconds of software setting this bit to a zero.
This field is zero if Port Power is zero.
5
R/WC
0
Over-current Change
Default = 0. This bit gets set to a one when there is a change to Over-current
Active. Software clears this bit by writing a one to this bit position.
4
R
0
Over-current Active
0 = This port does not have an over-current condition. 1 = This port currently
has an over-current condition. This bit will automatically transition from a
one to a zero when the over current condition is removed.
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