Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 507
causing the Control list processing to continue. If no TD is found on the
Control list, and if the HCD does not set ControlListFilled, then
ControlListFilled will still be 0 when HC completes processing the Control
list and Control list processing will stop.
0
R/W
R/E
0x0
HostControllerReset
This bit is by HCD to initiate a software reset of HC. Regardless of the
functional state of HC, it moves to the USBSuspend state in which most of
the operational registers are reset except those stated otherwise; e.g, the
InteruptRouting field of HcControl, and no Host bus accesses are allowed.
This bit is cleared by HC upon the completion of the reset operation. The
reset operation must be completed within 10 ms. This bit,
when set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.
8.5.2.6.4. HcInterruptStatus Register(Default Value: 0x00000000)
Offset: 0x40c
Register Name: HcInterruptStatus
Bit
Read/Write
Default/Hex
Description
HCD
HC
31:7
/
/
0x0
Reserved
6
R/W
R/W
0x0
RootHubStatusChange
This bit is set when the content of HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
R/W
R/W
0x0
FrameNumberOverflow
This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0
to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
4
R/W
R/W
0x0
UnrecoverableError
This bit is set when HC detects a system error not related to USB. HC should
not proceed with any processing nor signaling before the system error has
been corrected. HCD clears this bit after HC has been reset.
3
R/W
R/W
0x0
ResumeDetected
This bit is set when HC detects that a device on the USB is asserting resume
signaling. It is the transition from no resume signaling to resume signaling
causing this bit to be set. This bit is not set when HCD sets the USBRseume
state.
2
R/W
R/W
0x0
StartofFrame
This bit is set by HC at each start of frame and after the update of
HccaFrameNumber. HC also generates a SOF token at the same time.
1
R/W
R/W
0x0
WritebackDoneHead
This bit is set immediately after HC has written HcDoneHead to
HccaDoneHead. Further updates of the HccaDoneHead will not occur until
this bit has been cleared. HCD should only clear this bit after it has saved
the content of HccaDoneHead.
0
R/W
R/W
0x0
SchedulingOverrun
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