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Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 508
This bit is set when the USB schedule for the current Frame overruns and
after the update of HccaFrameNumber. A scheduling overrun will also
cause the SchedulingOverrunCount of HcCommandStatus to be
Incremented.
8.5.2.6.5. HcInterruptEnable Register(Default Value: 0x00000000)
Offset: 0x410
Register Name: HcInterruptEnable Register
Bit
Read/Write
Default/Hex
Description
HCD
HC
31
R/W
R
0x0
MasterInterruptEnable
A ‘0’ writtern to this field is ignored by HC. A ‘1’ written to this field enables
interrupt generation due to events specified in the other bits of this
register. This is used by HCD as Master Interrupt Enable.
30:7
/
/
0x0
Reserved
6
R/W
R
0x0
RootHubStatusChange Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Root Hub Status Change;
5
R/W
R
0x0
FrameNumberOverflow Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Frame Number Over Flow;
4
R/W
R
0x0
UnrecoverableError Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Unrecoverable Error;
3
R/W
R
0x0
ResumeDetected Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Resume Detected;
2
R/W
R
0x0
StartofFrame Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Start of Flame;
1
R/W
R
0x0
WritebackDoneHead Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Write back Done Head;
0
R/W
R
0x0
SchedulingOverrun Interrupt Enable
0
Ignore;
1
Enable interrupt generation due to Scheduling Overrun;
8.5.2.6.6. HcInterruptDisable Register(Default Value: 0x00000000)
Offset: 0x414
Register Name: HcInterruptDisable Register
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