Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 509
Bit
Read/Write
Default/Hex
Description
HCD
HC
31
R/W
R
0x0
MasterInterruptEnable
A written ‘0’ to this field is ignored by HC. A ‘1’ written to this field disables
interrupt generation due events specified in the other bits of this register.
This field is set after a hardware or software reset.
30:7
/
/
0x00
Reserved
6
R/W
R
0x0
RootHubStatusChange Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Root Hub Status Change;
5
R/W
R
0x0
FrameNumberOverflow Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Frame Number Over Flow;
4
R/W
R
0x0
UnrecoverableError Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Unrecoverable Error;
3
R/W
R
0x0
ResumeDetected Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Resume Detected;
2
R/W
R
0x0
StartofFrame Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Start of Flame;
1
R/W
R
0x0
WritebackDoneHead Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Write back Done Head;
0
R/w
R
0x0
SchedulingOverrun Interrupt Disable
0
Ignore;
1
Disable interrupt generation due to Scheduling Overrun;
8.5.2.6.7. HcHCCA Register(Default Value: 0x00000000)
Offset: 0x418
Register Name: HcHCCA
Bit
Read/Write
Default/Hex
Description
HCD
HC
31:8
R/W
R
0x0
HCCA[31:8]
This is the base address of the Host Controller Communication Area. This
area is used to hold the control structures and the Interrupt table that are
accessed by both the Host Controller and the Host Controller Driver.
7:0
R
R
0x0
HCCA[7:0]
The alignment restriction in HcHCCA register is evaluated by examining the
number of zeros in the lower order bits. The minimum alignment is 256
bytes, therefore, bits 0 through 7 must always return 0 when read.
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