Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 513
8.5.2.6.15. HcFmRemaining Register(Default Value: 0x00000000)
Offset: 0x438
Register Name: HcFmRemaining
Bit
Read/Write
Default/Hex
Description
HCD
HC
31
R
R/W
0x0
FrameRemaining Toggle
This bit is loaded from the FrameIntervalToggle field of HcFmInterval
whenever FrameRemaining reaches 0. This bit is used by HCD for the
synchronization between FrameInterval and FrameRemaining.
30:14
/
/
0x0
Reserved
13:0
R
RW
0x0
FramRemaining
This counter is decremented at each bit time. When it reaches zero, it is
reset by loading the FrameInterval value specified in HcFmInterval at the
next bit time boundary. When entering the USBOPERATIONAL state, HC
re-loads the content with the FrameInterval of HcFmInterval and uses the
updated value from the next SOF.
8.5.2.6.16. HcFmNumber Register(Default Value: 0x00000000)
Offset: 0x43c
Register Name: HcFmNumber
Bit
Read/Write
Default/Hex
Description
HCD
HC
31:16
Reserved
15:0
R
R/W
0x0
FrameNumber
This is incremented when HcFmRemaining is re-loaded. It will be rolled
over to 0x0 after 0x0ffff. When entering the USBOPERATIONAL state, this
will be incremented automatically. The content will be written to HCCA
after HC has incremented the FrameNumber at each frame boundary and
sent a SOF but before HC reads the first ED in that Frame. After writing to
HCCA, HC will set the StartofFrame in HcInterruptStatus.
8.5.2.6.17. HcPeriodicStart Register(Default Value: 0x00000000)
Offset: 0x440
Register Name: HcPeriodicStatus
Bit
Read/Write
Default/Hex
Description
HCD
HC
31:14
Reserved
13:0
R/W
R
0x0
PeriodicStart
After a hardware reset, this field is cleared. This is then set by HCD during
the HC initialization. The value is calculated roughly as 10% off from
HcFmInterval. A typical value will be 0x2A3F (0x3e67). When
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