Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 520
(write)SetPortSuspend
The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit. Writing
a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not
set PortSuspendStatus; instead it sets ConnectStatusChange. This informs
the driver that it attempted to suspend a disconnected port.
1
R/W
R/W
0x0
(read)PortEnableStatus
This bit indicates whether the port is enabled or disabled. The Root Hub
may clear this bit when an overcurrent condition, disconnect event,
switched-off power, or operational bus error such as babble is detected.
This change also causes PortEnabledStatusChange to be set. HCD sets this
bit by writing SetPortEnable and clears it by writing ClearPortEnable. This
bit cannot be set when CurrentConnectStatus is cleared. This bit is also
set, if not already, at the completion of a port reset when
ResetStatusChange is set or port suspend when
SuspendStatusChange is set.
0
port is disabled
1
port is enabled
(write)SetPortEnable
The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has no effect.
If CurrentConnectStatus is cleared, this write does not set
PortEnableStatus, but instead sets ConnectStatusChange. This informs the
driver that it attempted to enable a disconnected Port.
0
R/W
R/W
0x0
(read)CurrentConnectStatus
This bit reflects the current state of the downstream port.
0
No device connected
1
Device connected
(write)ClearPortEnable
The HCD writes a ‘1’ to clear the PortEnableStatus bit. Writing ‘0’ has no
effect. The CurrentConnectStatus is not affected by any write.
Note: This bit is always read ‘1’ when the attached device is
nonremovalble(DviceRemoveable[NumberDownstreamPort]).
8.5.2.7. HCI Interface Control and Status Register Description
8.5.2.7.1. HCI Interface Control Register(Default Value: 0x00000000)
Offset: 0x800
Register Name: HCI_ICR
Bit
R/W
Default/Hex
Description
31:21
/
/
Reserved.
20
R/W
0
EHCI HS force
Set 1 to this field force the ehci enter the high speed mode during bus reset.
This field only valid when the bit 1 is set.
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