Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 521
19:18
/
/
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17
R/W
0
HSIC Connect detect
1 in this field enable the hsic phy to detect device connect pulse on the bus.
This field only valid when the bit 1 is set.
16
R/W
0
HSIC Connect Interrupt Enable
Enable the HSIC connect interrupt.
This field only valid when the bit 1 is set.
15:13
/
/
/
12
/
/
/
11
R/W
0
AHB Master interface INCR16 enable
1: Use INCR16 when appropriate
0: do not use INCR16,use other enabled INCRX or unspecified length burst
INCR
10
R/W
0
AHB Master interface INCR8 enable
1: Use INCR8 when appropriate
0: do not use INCR8,use other enabled INCRX or unspecified length burst
INCR
9
R/W
0
AHB Master interface burst type INCR4 enable
1: Use INCR4 when appropriate
0: do not use INCR4,use other enabled INCRX or unspecified length burst
INCR
8
R/W
0
AHB Master interface INCRX align enable
1: start INCRx burst only on burst x-align address
0: Start burst on any double word boundary
Note: This bit must enable if any bit of 11:9 is enabled
7:2
/
/
Reserved
1
R/W
0
HSIC
0:/
1:HSIC
This meaning is only valid when the controller is HCI1.
0
R/W
0
ULPI bypass enable。
1: Enable UTMI interface, disable ULPI interface(SP used utmi
interface)
0: Enable ULPI interface, disable UTMI interface
8.5.2.7.2. HSIC status Register(Default Value: 0x00000000)
Offset: 0x804
Register Name: HSIC_STATUS
Bit
R/W
Default/Hex
Description
31:17
/
/
/
16
R/W
0
HSIC Connect Status
1 in this field indicates a device connect pulse being detected on the bus. This
field only valid when the EHCI HS force bit and the HSIC Phy Select bit is set.
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