Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 522
When the HSIC Connect Interrupt Enable is set, 1 in this bit will generate an
interrupt to the system.
This register is valid on HCI1.
15:0
/
/
/
8.5.2.8. USB Host Clock Requirement
Name
Description
HCLK
System clock (provided by AHB bus clock). This clock needs to be >30MHz.
CLK60M
Clock from PHY for HS SIE, is constant to be 60MHz.
CLK48M
Clock from PLL for FS/LS SIE, is constant to be 48MHz.
confidential