Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 523
8.6. I2S/PCM
8.6.1. Overview
The I2S/PCM Controller has been designed to transfer streaming audio-data between the system memory and the
codec chip. The controller supports standard I2S format, Left-justified Mode format, Right-justified Mode format, PCM
Mode format and TDM Mode format.
The I2S/PCM controller includes the following features:
 Supports industry-standard AMBA Peripheral Bus (APB) and it is fully compliant with the AMBA Specification,
Revision 2.0
 Support different sample period width in each interface when using LRCK and LRCKR at the same time
 Support full-duplex synchronous work mode
 Support Master / Slave mode
 Support adjustable interface voltage
 Support clock up to 100MHz
 Support adjustable audio sample rate from 8-bit to 32-bit.
 Support up to 8 slots which has adjustable width from 8-bit to 32-bit.
 Support sample rate from 8KHz to 192KHz
 Support 8-bits u-law and 8-bits A-law companded sample
 One 128 x 32-bit width FIFO for data transmit, one 64 x 32-bit width FIFO for data receive
 Support programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)
 Programmable FIFO thresholds
 Interrupt and DMA Support
 Support loopback mode for test
8.6.2. Signal Description
8.6.2.1. I2S/PCM Pin List
Signal Name(x=0,1)
Direction(M)
Description
PCMx_CLK
O
I2S/PCM x MCLK Output
PCMx_SYNC
I/O
I2S/PCM x Sample Rate Clock/Sync
PCMx_DIN
I
I2S/PCM x Serial Data Input
PCMx_DOUT
O
I2S/PCM x Serial Data Output
8.6.2.2. Digital Audio Interface Clock Source and Frequency
Name
Description
confidential