Owners manual

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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 525
BCLK
LRCK
DOUT/DIN
n-1
…
1
0
n-2
MSB LSB
Left Channel
Right Channel
1 / fs
8 slot
4 slot
2 slot
0 1
0
0
1
1
2
2
3
3
4
6
5 7
DOUT/DIN
DOUT/DIN
[I2S mode]
m m = 0 ~ 7
slot
sample
[TDM-I2S mode]
[TDM-I2S mode]
Figure 8-9. Timing Diagram for I2S/TDM-I2S mode
BCLK
LRCK
n-1
…
1
0
n-2
MSB LSB
Left Channel
Right Channel
1 / fs
8 slot
4 slot
2 slot
0 1
0
0
1
1
2
2
3
3
4 6
5 7
[Left-Justified mode]
m m = 0 ~ 7
slot
sample
[TDM-Left mode]
[TDM-Left mode]
Figure 8-10. Timing Diagram for Left-justified/TDM-Left mode
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