Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 526
BCLK
LRCK
n-1
…
1
0
n-2
MSB LSB
Left Channel
Right Channel
1 / fs
8 slot
4 slot
2 slot
0
1
0
0
1
1
2
2
3
3
4 6
5 7
[Right-Justified mode]
m m = 0 ~ 7
slot
sample
[TDM-Right mode]
[TDM-Right mode]
Figure 8-11. Timing Diagram for Right-justified/TDM-Right mode
BCLK
LRCK
n-1
…
1
0
n-2
MSB LSB
1 / fs
8 slot
4 slot
2 slot
0
1
2 3
[DSP_B stereo]
m m = 0 ~ 7
slot
sample
[TDM-DSP_B mode]
[TDM-DSP_B mode]
4
5
6 7
0
1
2 3
0
1
[DSP_B mono]
1 slot
0
0
1
2 3 4
5
6 7
0
1
2 3
0
1
0
8 slot
4 slot
2 slot
[DSP_A stereo]
[TDM-DSP_A mode]
[TDM-DSP_A mode]
[DSP_A mono]
1 slot
Figure 8-12. Timing Diagram for PCM/TDM-PCM mode
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