Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 528
8.6.6. I2S/PCM Register List
Module Name
Base Address
I2S/PCM 0
0x01C22000
I2S/PCM 1
0x01C22400
I2S/PCM 2
0x01C22800 (for HDMI)
Register Name
Offset
Description
I2S/PCM_CTL
0x00
I2S/PCM Control Register
I2S/PCM_FMT0
0x04
I2S/PCM Format Register 0
I2S/PCM_FMT1
0x08
I2S/PCM Format Register 1
I2S/PCM_ISTA
0x0C
I2S/PCM Interrupt Status Register
I2S/PCM_RXFIFO
0x10
I2S/PCM RX FIFO Register
I2S/PCM_FCTL
0x14
I2S/PCM FIFO Control Register
I2S/PCM_FSTA
0x18
I2S/PCM FIFO Status Register
I2S/PCM_INT
0x1C
I2S/PCM DMA & Interrupt Control Register
I2S/PCM_TXFIFO
0x20
I2S/PCM TX FIFO Register
I2S/PCM_CLKD
0x24
I2S/PCM Clock Divide Register
I2S/PCM_TXCNT
0x28
I2S/PCM TX Sample Counter Register
I2S/PCM_RXCNT
0x2C
I2S/PCM RX Sample Counter Register
I2S/PCM_CHCFG
0x30
I2S/PCM Channel Configuration register
I2S/PCM_TX0CHCFG
0x34
I2S/PCM TX0 Channel Configuration register
I2S/PCM_TX1CHSEL
0x38
I2S/PCM TX1 Channel Select Register
I2S/PCM_TX2CHSEL
0x3C
I2S/PCM TX2 Channel Select Register
I2S/PCM_TX3CHSEL
0x40
I2S/PCM TX3 Channel Select Register
I2S/PCM_TX0CHMAP
0x44
I2S/PCM TX0 Channel Mapping Register
I2S/PCM_TX0CHMAP
0x48
I2S/PCM TX1 Channel Mapping Register
I2S/PCM_TX0CHMAP
0x4C
I2S/PCM TX2 Channel Mapping Register
I2S/PCM_TX0CHMAP
0x50
I2S/PCM TX3 Channel Mapping Register
I2S/PCM_RXCHSEL
0x54
I2S/PCM RX Channel Select register
I2S/PCM_RXCHMAP
0x58
I2S/PCM RX Channel Mapping Register
8.6.7. I2S/PCM Register Description
8.6.7.1. I2S/PCM Control Register(Default Value: 0x00060000)
Offset: 0x00
Register Name: I2S/PCM_CTL
Bit
R/W
Default/Hex
Description
31:19
/
/
/
18
R/W
1
BCLK_OUT
0: input
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