Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 529
1: output
17
R/W
1
LRCK_OUT
0: input
1: output
16
R/W
0
LRCKR_OUT
0: input
1: output
15:12
/
/
/
11
R/W
0
/
10
R/W
0
/
9
R/W
0
/
8
R/W
0
SDO0_EN
0: Disable, Hi-Z state
1: Enable
7
/
/
/
6
R/W
0
OUT Mute
0: normal transfer
1: force DOUT to output 0
5:4
R/W
0
MODE_SEL
Mode Selection
0: PCM mode (offset 0: DSP_B; offset 1: DSP_A)
1: Left mode (offset 0: LJ mode; offset 1: I2S mode)
2: Right-Justified mode
3: Reserved
3
R/W
0
LOOP
Loop back test
0: Normal mode
1: Loop back test
When set ‘1’, connecting the SDO0 with the SDI
2
R/W
0
TXEN
Transmitter Block Enable
0: Disable
1: Enable
1
R/W
0
RXEN
Receiver Block Enable
0: Disable
1: Enable
0
R/W
0
GEN
Globe Enable
A disable on this bit overrides any other block or channel enables.
0: Disable
1: Enable
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