Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 531
Sample Resolution
0: Reserved
1: 8-bit
2: 12-bit
3: 16-bit
4: 20-bit
5: 24-bit
6: 28-bit
7: 32-bit
3
R/W
0
EDGE_TRANSFER
0: SDO drive data and SDI sample data at the different BCLK edge
1: SDO drive data and SDI sample data at the same BCLK edge
BCLK_POLARITY = 0, use negative edge
BCLK_POLARITY = 1, use positive edge
2:0
R/W
0x3
SW
Slot Width Select
0: Reserved
1: 8-bit
2: 12-bit
3: 16-bit
4: 20-bit
5: 24-bit
6: 28-bit
7: 32-bit
8.6.7.3. I2S/PCM Format Register1 (Default Value: 0x00000030)
Offset: 0x08
Register Name: I2S/PCM_FMT1
Bit
R/W
Default/Hex
Description
31:8
/
/
7
R/W
0
RX MLS
MSB / LSB First Select
0: MSB First
1: LSB First
6
R/W
0
TX MLS
MSB / LSB First Select
0: MSB First
1: LSB First
5:4
R/W
3
SEXT
Sign Extend in slot [sample resolution < slot width]
0: Zeros or audio gain padding at LSB position
1: Sign extension at MSB position
2: Reserved
3: Transfer 0 after each sample in each slot
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