Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 532
3:2
R/W
0
RX_PDM
PCM Data Mode
0: Linear PCM
1: reserved
2: 8-bits u-law
3: 8-bits A-law
1:0
R/W
0
TX_PDM
PCM Data Mode
0: Linear PCM
1: reserved
2: 8-bits u-law
3: 8-bits A-law
8.6.7.4. I2S/PCM Interrupt Status Register(Default Value: 0x00000010)
Offset: 0x0C
Register Name: I2S/PCM_ISTA
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6
R/W
0
TXU_INT
TX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1: FIFO Under run Pending Interrupt
Write 1 to clear this interrupt
5
R/W
0
TXO_INT
TX FIFO Overrun Pending Interrupt
0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt
4
R/W
1
TXE_INT
TX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt when data in TX FIFO are less than TX
trigger level
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.
3
/
/
/
2
R/W
0
RXU_INT
RX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1:FIFO Under run Pending Interrupt
Write 1 to clear this interrupt
1
R/W
0
RXO_INT
RX FIFO Overrun Pending Interrupt
0: No Pending IRQ
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