Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 533
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt
0
R/W
0
RXA_INT
RX FIFO Data Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ when data in RX FIFO are more than RX
trigger level
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.
8.6.7.5. I2S/PCM RX FIFO Register(Default Value: 0x00000000)
Offset: 0x10
Register Name: I2S/PCM_RXFIFO
Bit
R/W
Default/Hex
Description
31:0
R
0
RX_DATA
RX Sample
Host can get one sample by reading this register. The left channel sample
data is first and then the right channel sample.
8.6.7.6. I2S/PCM FIFO Control Register (Default Value: 0x000400F0)
Offset: 0x14
Register Name: I2S/PCM_FCTL
Bit
R/W
Default/Hex
Description
31
R/W
0
HUB_EN
Audio hub enable
0:disable
1:enable
30:26
/
/
/
25
R/W
0
FTX
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
24
R/W
0
FRX
Write ‘1’ to flush RX FIFO, self clear to ‘0’.
23:19
/
/
/
18:12
R/W
0x40
TXTL
TX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for TXFIFO normal condition
Trigger Level = TXTL
11:10
/
/
/
9:4
R/W
0xF
RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RXFIFO normal condition
Trigger Level = RXTL + 1
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