Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 535
8.6.7.8. I2S/PCM DMA & Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: I2S/PCM_INT
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0
TX_DRQ
TX FIFO Empty DRQ Enable
0: Disable
1: Enable
6
R/W
0
TXUI_EN
TX FIFO Under run Interrupt Enable
0: Disable
1: Enable
5
R/W
0
TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, an interrupt happens when writing new audio data if TX
FIFO is full.
4
R/W
0
TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable
3
R/W
0
RX_DRQ
RX FIFO Data Available DRQ Enable
0: Disable
1: Enable
When set to ‘1’, RXFIFO DMA Request line is asserted if Data is available in
RX FIFO.
2
R/W
0
RXUI_EN
RX FIFO Under run Interrupt Enable
0: Disable
1: Enable
1
R/W
0
RXOI_EN
RX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
0
R/W
0
RXAI_EN
RX FIFO Data Available Interrupt Enable
0: Disable
1: Enable
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