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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 536
8.6.7.9. I2S/PCM TX FIFO Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: I2S/PCM_TXFIFO
Bit
R/W
Default/Hex
Description
31:0
W
0
TX_DATA
TX Sample
Transmitting left, right channel sample data should be written this register
one by one. The left channel sample data is first and then the right channel
sample.
8.6.7.10. I2S/PCM Clock Divide Register(Default Value: 0x00000000)
Offset: 0x24
Register Name: I2S/PCM_CLKD
Bit
R/W
Default/Hex
Description
31:9
/
/
/
8
R/W
0
MCLKO_EN
0: Disable MCLK Output
1: Enable MCLK Output
Notes: Whether in Slave or Master mode, when this bit is set to 1, MCLK
should be output.
7:4
R/W
0
BCLKDIV
BCLK Divide Ratio from PLL2
0: reserved
1: Divide by 1
2: Divide by 2
3: Divide by 4
4: Divide by 6
5: Divide by 8
6: Divide by 12
7: Divide by 16
8: Divide by 24
9: Divide by 32
10: Divide by 48
11: Divide by 64
12: Divide by 96
13: Divide by 128
14: Divide by 176
15: Divide by 192
3:0
R/W
0
MCLKDIV
MCLK Divide Ratio from PLL2 Output
0: reserved
1: Divide by 1
2: Divide by 2
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