Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 538
Bit
R/W
Default/Hex
Description
31:10
/
/
/
9
R/W
0
TX_SLOT_HIZ
0: normal mode for the last half cycle of BCLK in the slot
1: turn to hi-z state for the last half cycle of BCLK in the slot
8
R/W
0
TXn_STATE
0: transfer level 0 when not transferring slot
1: turn to hi-z state when not transferring slot
7
/
/
/
6:4
R/W
0
RX_SLOT_NUM
RX Channel/Slot Number which between CPU/DMA and FIFO
0: 1 channel or slot
...
7: 8 channels or slots
3
/
/
/
2:0
R/W
0
TX_SLOT_NUM
TX Channel/Slot Number which between CPU/DMA and FIFO
0: 1 channel or slot
...
7: 8 channels or slots
8.6.7.14. I2S/PCM TXn Channel Select Register(Default Value: 0x00000000)
Offset: 0x34 + n*4 (n = 0, 1, 2, 3)
Register Name: I2S/PCM_TXnCHSEL
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13:12
R/W
0
TXn_OFFSET
TXn offset tune, TXn data offset to LRCK
0: no offset
n: data is offset by n BCLKs to LRCK
11:4
R/W
0
TXn_CHEN
TXn Channel (slot) enable, bit[11:4] refer to slot [7:0]. When one or more
slot(s) is(are) disabled, the affected slot(s) is(are) set to disable state
0: disable
1: enable
3
/
/
/
2:0
R/W
0
TXn_CHSEL
TXn Channel (slot) number Select for each output
0: 1 channel / slot
…
7: 8 channels / slots
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