Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 546
1
R/W
0
GEN
Globe Enable
A disable on this bit overrides any other block or channel enables and
flushes all FIFOs.
0: Disable
1: Enable
0
R/W
0
RST
Reset
0: Normal
1: Reset
Self clear to 0
8.7.4.2. OWA TX Configure Register(Default Value: 0x000000F0)
Offset: 0x04
Register Name: OWA_TX_CFIG
Bit
R/W
Default/Hex
Description
31
R/W
0
TX_SINGLE_MODE
Tx single channel mode
0: Disable
1: Eanble
30:18
/
/
/
17
R/W
0
ASS
Audio sample select with TX FIFO under run
when
0: sending 0
1: sending the last audio
Note: This bit is only valid in PCM mode
16
R/W
0
TX_AUDIO
TX data type
0: Linear PCM (Valid bit of both sub-frame set to 0 )
1: Non-audio(Valid bit of both sub-frame set to 1)
15:9
/
/
/
8:4
R/W
0xF
TX_RATIO
TX clock divide Ratio
Note: clock divide ratio = TX TATIO +1
3:2
R/W
0
TX_SF
TX Sample format:
00: 16bit
01: 20bit
10: 24bit
11: Reserved
1
R/W
0
TX_CHM
CHSTMODE
0: Channel status A&B set to 0
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